A DUAL MODULATION PULSE POSITION MODULATION APPROACH IN 130NM CMOS TECHNOLOGY FOR TIME BASED SERIAL COMMUNICATION LINKS

Salah Rashdan, Mostafa; M. Sobhy, Nesma; El-Sawy, Ahmed

doi:10.21608/jaet.2020.73033

A DUAL MODULATION PULSE POSITION MODULATION APPROACH IN 130NM CMOS TECHNOLOGY FOR TIME BASED SERIAL COMMUNICATION LINKS

Authors

¹ Electrical Engineering Dept, Faculty of Engineering, Aswan

² Electrical Engineering Dept., Faculty of Engineering, Minia University

10.21608/jaet.2020.73033

Abstract

A time-based serial data link architecture that involves dual modulation Pulse Position Modulation approach (DMPPM) is presented in this paper. In the proposed approach, both the rising and falling edges of the input clock signal are modulated independently. Using the proposed approach allows increasing the total number of transmitted bits without significantly affecting the modulated signal bandwidth. A 6-bit 4.8 Gb/s DMPPM link design example has been designed and simulated based on the proposed approach in 130nm CMOS technology. An 800MHz has been used as an input clock signal. The simulation results and a comparison between the proposed link and other serial links are presented. The power consumption of the transmitter and the receiver circuits are less than 100mW.

Keywords

Main Subjects

Electrical Engineering.

References

[1] P. K. Hanumolu, G.-Y. Wei, and U.-K. Moon, "Equalizers for high-speed serial links," International journal of high speed electronics and systems, vol. 15, pp. 429-458, 2005.

[2] X. Wang and Q. Hu, "Analysis and optimization of combined equalizer for high speed serial link," in Anti-counterfeiting, Security, and Identification (ASID), 2015 IEEE 9th International Conference on, 2015, pp. 43-46.

[3] A. Jain, "Equalization in continuous and discrete time for high speed links using 65 nm technology," 2016.

[4] V. Stojanović, "Channel-limited high-speed links: Modeling, analysis and design," PhD. Thesis, 2004.

[5] B. Song, K. Kim, J. Lee, and J. Burm, "A 0.18-μm CMOS 10-Gb/s Dual-Mode 10-PAM Serial Link Transceiver," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, pp. 457-468, 2013.

[6] W.-H. Chen, G.-K. Dehang, J.-W. Chen, and S.-I. Liu, "A CMOS 400-Mb/s serial link for AS-memory systems using a PWM scheme," IEEE Journal of Solid-State Circuits, vol. 36, pp. 1498-1505, 2001.

[7] N. Ghaderi, Z. D. Ghol, and S. R. Fatemi, "A CMOS 7Gb/s, 4-PAM and 4-PWM, serial link transceiver," Analog Integrated Circuits and Signal Processing, vol. 89, pp. 809-823, 2016.

[8] M. Rashdan, A. Yousif, J. Haslett, and B. Maundy, "A new time-based architecture for serial communication links," in Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on, 2009, pp. 531-534.

[9] M. Rashdan, A. Yousif, J. Haslett, and B. Maundy, "Data link design using a time-based approach," in Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, 2010, pp. 3977-3980.

[10] M. Rashdan, "Dual-time resolution time-based transceiver for low-power serial interfaces," Analog Integrated Circuits and Signal Processing, vol. 92, pp. 81-89, 2017.

[11] W. Bae, C.-S. Yoon, and D.-K. Jeong, "A low-power pulse position modulation transceiver," in Circuits and Systems (ISCAS), 2015 IEEE International Symposium on, 2015, pp. 1614-1617.

[12] M. Rashdan, A. Yousif, J. Haslett, and B. Maundy, "Differential Time Signaling Data-Link Architecture," Journal of Signal Processing Systems, vol. 70, pp. 21-37, 2013.

[13] A. Yousif, M. Rashdan, J. Haslett, and B. Maundy, "A low power and high speed PPM design for ultra wideband communications," in Electrical and Computer Engineering, 2008. CCECE 2008. Canadian Conference on, 2008, pp. 001055-001058.

[14] J. Yu, F. F. Dai, and R. C. Jaeger, "A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13CMOS Technology," IEEE journal of solid-state circuits, vol. 45, pp. 830-842, 2010.

[15] M. Zanuso, P. Madoglio, S. Levantino, C. Samori, and A. L. Lacaita, "Time-to-digital converter for frequency synthesis based on a digital bang-bang DLL," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, pp. 548-555, 2010.

[16] A. Yousif and J. W. Haslett, "A Fine Resolution TDC Architecture For Next Generation Pet Imaging," IEEE Transactions on Nuclear Science, vol. 54, pp. 1574–1582, October 2007.

[17] C.-Y. Yang and Y. Lee, "A PWM and PAM signaling hybrid technology for serial-link transceivers," IEEE Transactions on Instrumentation and Measurement, vol. 57, pp. 1058-1070, 2008.

[18] W. Madany, M. Rashdan, and E.-S. Hasaneen, "Pulse-position and pulse-amplitude modulation interface for serial data link applications," in Electronics, Communications and Computers (JEC-ECC), 2016 Fourth International Japan-Egypt Conference on, 2016, pp. 95-98.