Development and Implementation of pipeline Convolutional Coding using FPGA

Hassan, Sara M.; Hussein, Aziza I.; Khalaf, Ashraf Abdelmonem

doi:10.21608/jaet.2024.294711.1290

Development and Implementation of pipeline Convolutional Coding using FPGA

Document Type : Original Article

Authors

¹ Electronics and Communications Engineering Dep., Modern Academy for Engineering and Technology, Cairo, Egypt

² Electrical and Computer Engineering Dep., Effat University, Jeddah, KSA

³ Electrical Engineering Dep., Faculty of Engineering, Minia University, Minia, Egypt

10.21608/jaet.2024.294711.1290

Abstract

Channel coding is essential for ensuring reliable data transmission in challenging wireless communications. Improving spectrum efficiency involves leveraging efficient forward error correction (FEC) methods. Viterbi decoding plays a critical role in Convolutional channel coding for accurate error detection and correction, particularly in LTE and Satellite communication systems. This article discusses the simulation and FPGA implementation of a newly proposed non-systematic Convolutional system featuring a block interleaver and 64-QAM Mapping under AWGN and Rayleigh channel conditions. The system adopts a Convolutional coding rate of 1/3 and a constraint length of 7, utilizing a Trellis diagram for encoding and the Viterbi algorithm for decoding with hard decision decoding. Additionally, a pipeline coding approach is employed. Simulations are conducted using MATLAB-R2023b, and the implementation is executed on Virtex 6 (XC6VLX240T) FPGA using Xilinx 14.7. The study reveals that the pipeline technique demands more FPGA resources compared to traditional methods while still utilizing a small resource block from Virtex 6, with 3% and 9% usage of slice registers and LUTs, respectively. Moreover, the system's timing is reduced from 24 to 14 clock cycles, enhancing the efficiency of entirely LUT-FF pairs from 55% to 63%.

Keywords